Four different versions of the JTAG TAP core are included, targeting four different types of system. ![]() The second component is a JTAG TAP this relatively small hardware core acts as a connection between the adv_dbg_if core and the external pins of the target chip (ASIC or FPGA). The first component, the "adv_dbg_if" core, is a hardware core designed to interface directly to the OR1200 CPU and a WishBone bus, controlling the CPU and reading and writing data to both the CPU registers and memory addresses on the bus. In particular, target systems using the OpenRISC 1200 processor and a WishBone bus are currently supported by the Advanced Debug Interface. The Advanced Debug Interface is a suite of IP cores and software programs designed to allow a developer to download code to a target CPU in a System-on-Chip, then perform source-level debugging of that code.
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